The scaling of VLSI circuits is a constant effort. With circuits becoming smaller and faster, device drive current improvement becomes more important. Among efforts being made to improve device drive current, forming a stressed silicon channel, thus enhancing carrier mobility, is a known practice. Stress, sometimes referred to as strain, can enhance electron and hole mobility. The performance of a MOS device can be enhanced through a stressed-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
Stress can be induced by forming a stressed contact etch stop (CES) layer on a MOS device. When a CES layer is deposited, because of the difference in bonding energy between the CES layer and the underlying layer, an in-plane stress develops to achieve energy conservation for the composite layer, the CES layer and the underlying layer. In the channel region, stress also develops as a response to the stress applied, and the carrier mobility is enhanced. Stress applied to the channel region is determined by the intrinsic stress in the CES layer and its thickness, and the intrinsic stress generally increases when the thickness of the CES layer increases.
While thick CES layers are desirable for stress engineering, very thick CES layers cause difficulty in subsequent processes, such as inter-layer dielectric (ILD) gap filling, and therefore are undesired in high-density circuit design. Methods to improve the efficiency of applying stress using a CES layer have thus been explored. U.S. Pat. No. 6,870,179 discusses a method for improving stress without the necessity of increasing the thickness of the CES layer. As shown in FIG. 1, after the formation of spacers 120, an extra recessing step is performed on the substrate 104 along edges of spacers 120, forming recesses 106. A stressed CES layer 108 is then formed. Due to recesses 106, the stress applied on channel region 110 by CES layer 108 increases.
Drive current improvement using such a method is significant for large devices. For small devices, however, particularly devices manufactured using 65 nm technologies and beyond, the drive current improvement is less observable, even though the carrier mobility in the channel region is improved. A possible reason is that the recessing of the source/drain regions 114 causes current crowding effects in regions 118, which are substantially narrow, and the device drive current is degraded accordingly. The current crowding effects are particularly severe in small devices having shallow junctions. Additionally, narrow regions 118 cause the leakage current to increase.
What is needed, therefore, is a method that optimizes the stress applied to the channel region while eliminating the detrimental current crowding effects and leakage current, so that device drive currents are improved.